Technical Field
This invention relates to a semiconductor device.
Background Art
It is expected that semiconductor materials such as silicon carbide (SiC), gallium nitride (GaN), and diamond, which have band gaps wider than silicon (hereinafter, described as wide band gap semiconductors), are applied to power devices especially because of excellent characteristics such as a high dielectric breakdown field and high thermal conductivity. For conventional power devices, for example, a vertical MOSFET (metal oxide field effect transistor) fabricated by using SiC (hereinafter, SiC vertical MOSFET), will be described. FIG. 14 is a sectional view illustrating a structure of the conventional SiC vertical MOSFET.
As shown in FIG. 14, in the conventional SiC vertical MOSFET, an n− drift region 102, which is formed by epitaxial growth, is disposed on the front surface of an n+ semiconductor substrate 101 to be an n+ drain region. A p-channel region 103 is selectively disposed on a surface layer of the n− drift region 102 in which the surface layer is located at the side opposite to the n+ semiconductor substrate 101. Inside the n− drift region 102, a high-concentration p+ base region 104 is disposed so as to adjoin the p-channel region 103 at the lower part of the p-channel region 103 (the n+ semiconductor substrate 101 side).
The high-concentration p+ base region 104 has a function to prevent the p-channel region 103 from punch-through if a reverse bias is highly applied on the pn junction between the p-channel region 103 and the n− drift region 102. An n+ source region 105 and a p+ contact region 106 are selectively disposed inside the p-channel region 103. A gate electrode 108 is disposed through a gate dielectric film 107 on the surface stretching from one to the other of the parts sandwiched between the n+ source region 105 and the n− drift region 102 in each of the p-channel regions 103 via the surface of the n− drift region 102 next to the both parts.
It is known that inside the n− drift region 102, a junction field effect transistor (JFET) region 102a sandwiched by high-concentration p+ base regions 104 next to each other has an impurity concentration higher than the other part of the n− drift region 102 in order to reduce the JFET resistance. A source electrode 109 contacts with the n+ source region 105 and the p+ contact region 106. A drain electrode 110 is disposed on the back surface of the n+ semiconductor substrate 101.
Next, basic operation of the SiC vertical MOSFET will be described. In the off-state, if a high voltage, which is higher than an electric potential of the source electrode 109, is applied on a drain electrode 110, the junction formed between the n− drift region 102 and the p-channel region 103 is reverse-biased to form a blocking state. In the state, if a voltage that is equal to or higher than the threshold is applied on the gate electrode 108, charges begin to be accumulated in the gate electrode 108. Simultaneously, an area adjoining the gate dielectric film 107 in the p-channel region 103 is inverted to form an n-channel region (not shown).
Forming the n-channel region at the place between the n+ source region 105 and the n− drift region 102 causes the reverse biased junction to disappear on the passage that passes the n-channel region. Then this forms an electron pathway that passes the source electrode 109, the n+ source region 105, the n-channel region, the n− drift region 102, the n+ semiconductor substrate 101, and the drain electrode 110. Thus this allows a current to flow from the drain electrode 110 to the source electrode 109. That is, the SiC vertical MOSFET is turned into the on-state.
On the other hand, if a voltage applied between the source electrode 109 and gate electrode 108 becomes smaller than the threshold, charges accumulated in the gate electrode 108 are discharged. Then this permits the n-channel region inverted to n-type in the p-channel region 103 to return to p-type and then to disappear. Therefore, the electron pathway connected from the drain electrode 110 to the source electrode 109 vanishes away, and no current flows. Thus the SiC vertical MOSFET is turned into the off-state.
As described above, the basic operation of the SiC vertical MOSFET is not different from that of a Si MOSFET manufactured using Si. But, as described earlier, the wide band gap semiconductor has higher dielectric breakdown field intensity in comparison with Si (approximately 10 times higher for 4H—SiC, 11 times for GaN, and 19 times for diamond). Then this allows the impurity concentration to increase in the n− drift region 102, and permits the thickness to decrease in the n− drift region 102 for the SiC vertical MOSFET. Thus it is possible to realize both high breakdown voltage and low on-state resistance.
As described above, a MOSFET fabricated using the wide band gap semiconductor has a high dielectric breakdown field intensity. Then this allows the impurity concentration to increase (allows the resistance to decrease) in the n− drift region 102. And then, increasing the impurity concentration of the n− drift region 102 allows the extension of the depletion layer to decrease from the pn junction formed between the p-channel region 103 and the n− drift region 102 to the n− drift region 102 side. Then this allows a minimum required thickness of the n− drift region 102 to decrease in order to realize a predetermined breakdown voltage. Thus it is possible to reduce the on-state resistance further.
As such a semiconductor device fabricated using the wide band gap semiconductor, in the SiC vertical MOSFET fabricated by a method that a channel region is formed using a low concentration p-type epitaxial layer whose conductivity type is inverted from p-type to n-type by performing ion implantation to form an electron guide path (an inverted layer), there is provided a device that a second inverted layer is disposed at the position approximately equivalent distance on right and left sides from the inverted layer, and the source layers on right and left sides are formed so that each of the inside edges thereof is positioned inside the second inverted layer (for example, see the following Patent literature 1).
Patent literature 1: Japanese Patent No. 5071763
However, if a voltage that is equal to or higher than the threshold is applied on the gate electrode 108, a current that flows through an inversion layer (an n-channel region) formed at the surface of the p-channel region 103 flows from the drain electrode 110 to the JFET region 102a via the n+ semiconductor substrate 101 and the n− drift region 102. At the time, most of the current flows to a high current density part 102b, which is sandwiched between the JFET region 102a and the n+ semiconductor substrate 101, in the n− drift region 102.
On the other hand, a low current density part 102c, which is sandwiched between the high-concentration p+ base region 104 and the n+ semiconductor substrate 101, in the n− drift region 102 results in an ineffective region where any current hardly flows. FIG. 14 shows approximately the high current density part 102b and the low current density part 102c in the n− drift region 102. If the ineffective region is formed in the n− drift region 102 as described above, resistance of the n− drift region 102 increases unexpectedly owing to so-called spreading resistance.
The thinner the thickness of the n− drift region 102 becomes, the more remarkably the problem that the resistance of the n− drift region 102 increases owing to the ineffective region formed in the n− drift region 102 appears. Then this causes features obtained by employing the wide band gap semiconductor to be lost. The problem may be resolved so that when using micro-fabrication technology, the widths of the high-concentration p+ base regions 104 are narrowed, and also the spaces are narrowed among a plurality of the JFET regions 102a. 
However, there is a limit for reducing the size of the high-concentration p+ base region 104. Further, if a width of the JFET region 102a should widen, an effect that relaxes an electric field applied on the gate dielectric film 107 will decline, wherein the effect is obtained because the JFET region 102a is pinched-off by the depletion layer extending from the pn junction between the high-concentration p+ base region 104 and the n− drift region 102 to the n− drift region 102 side. And then this causes adverse effects such as oxide film breakage and the breakdown voltage lowering. Along with this, there is a new problem that the on-state voltage increases owing to cell density decline.
In order to solve the problems in the conventional art described above, it is an object of the invention to provide a semiconductor device having high breakdown voltage. Further, in order to solve the problems in the conventional art described above, it is another object of the invention to provide a semiconductor device having low on-state resistance.